12.2 GHz All-digital PLL with Pattern Memorizing Cells for Low Power/low Jitter using 65 nm CMOS Process

A system level power/jitter reduction technique of all-digital phase locked loop (ADPLL) design has been developed. The architecture to memorize the repetitive control signal pattern of digitally-controlled oscillator (DCO) during lock state and to regenerate the pattern, achieve the reduced power consumption compared to conventional mode from 14.4 mW to 9.51 mW in 1.0 V supply at 12.2 GHz and concurrently reduce jitter from 1.86 ps to 1.56 ps. The prototype PLL has been fabricated in 65 nm CMOS process and occupies 0.16 mm(2) chip area.