Reliability evaluation of ultra thin 3D-IC package under the coupling load effects of the manufacturing process and temperature cycling test

In the development of semiconductor packaging technology from planar to three-dimensional vertical integration, chip interconnection density has increased, and the distance of signal transmission has dropped to improve overall device performance. In this research, an architecture composed of through‑silicon via (TSV) and solder microbump (μbump) is utilized to assemble an ultra thin-type chip into a three-dimensional integrated circuit (3D-IC) package. To explore the influence of residual thermomechanical residual stress induced during the manufacture of the 3D-IC package on the subsequent reliability of the thermal cycling test (TCT), this study establishes a nonlinear simulation methodology for investigating the coupling effect of the manufacturing process and the TCT. The plastic and creep behaviors of the solder μbump are considered in the finite element modeling. The concerned geometric dimensions and underfill materials are also parametrically analyzed. Furthermore, the inelastic strain accumulated in the crucial SnAg solder μbump is examined. Results indicate that the residual strain in the manufacturing process causes an obvious packaging warpage and converges at the subsequent TCT stage. The creep of the solder μbump increases up to 50% in thermal cycling, thereby highlighting the importance of considering the creep model. Moreover, the parameterization of chip thickness can minimize the inelastic strain increment of the solder μbump, and the low Young's modulus of the underfill materials exerts a significant effect on the warpage of the packaging module and the stress compliance of the μbumps.