A Dual-Input, Digital Hybrid Buck-LDO System Featuring Fast Load Transient Response, Zero-Wire Current Handover & Input PDN Resonance Reduction

Khondker Zakir Ahmed, Nachiket V. Desai,Harish K. Krishnamurthy,Sheldon Weng,Xiaosen Liu,Krishnan Ravichandran,James W. Tschanz,Vivek De

2021 Symposium on VLSI Circuits（2021）

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摘要

A dual-input, digital hybrid buck-LDO system featuring 300MHz Fully-Integrated Voltage Regulator (FIVR) and Computational Transient Management Controller (CTMC) based Low Dropout (LDO) regulator is presented. The high speed, parallel CTMC-LDO reduces the FIVR input resonance (82% pk-to-pk voltage-swing reduction). The CTMC-LDO operates without any communication with FIVR and can act as a clamp (54% droop & 69% settling time reduction) or share current (0-100%) in parallel with the FIVR, thus increasing load capacity.

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关键词

low dropout regulator,parallel CTMC-LDO,FIVR input resonance,pk-to-pk voltage-swing reduction,dual-input,zero-wire current handover,300MHz fully-integrated voltage regulator,computational transient management controller,input PDN resonance reduction,digital hybrid buck-LDO system,fast load transient response,frequency 300.0 MHz

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