An Instruction-Level Power and Energy Model for the Rocket Chip Generator

As digital systems become more power and energy constrained, the need for optimizing these quantities early in the design process grows ever more important. Fast and accurate power and energy models are needed for complex hardware blocks, such as processor cores, in order to optimize systems that contain these blocks. Today accurate energy/power estimation can be achieved only after physical design is complete, which is too late to affect the system architecture. This paper demonstrates the development of a fast instruction-level model for the Rocket Chip Generator to facilitate power- and energy-efficient software optimization. We first discuss an event-based power modeling methodology which is the foundation of our model and is compatible with emerging power- and energy-modeling standards such as IEEE-2416. Detailed energy characterization for basic events is explained along with an evaluation of a model with and without cache-fill events. The validation results show that the proposed instruction-level power model achieves less than 3% error on simple C program benchmarks.