A Low-Power Double-Tail f(T)-Doubler Comparator in 65-nm CMOS

This paper presents a novel low power double tail latched comparator for emerging high-speed internet of things (IoT) applications. The comparator is designed in a standard 65-nm complementary metal oxide semiconductor (CMOS) process and occupies 87.7 mu m(2). It employs f(T)-doubler topology which reduces the device capacitances, allowing faster switching and lower power. When connected to a 600-mV supply and clocked at 20 MHz, the post-layout simulations show that the proposed comparator achieves 11% smaller delay and 13% lower power than the conventional design. The proposed comparator demonstrates good performance with comparable power to the state-of-the-art designs when normalized to frequency.