Cache-accel: FPGA Accelerated Cache Simulator with Partially Reconfigurable Prefetcher

Computer architects need to choose the design configurations which will work effectively across most commonly used workloads. Design space exploration of caches enables the architect to choose the right configuration based on metrics such as hit rates, power, area, and timing. Although the idea of a cache simulator is not new, the hardware/FPGA implementation of such simulators has not been well e...