3D Electro-optical Simulations for Improving the Photon Detection Probability of SPAD Implemented in FD-SOI CMOS Technology

In this article, a 3D electro-optical simulation method is presented in order to estimate the Photon Detection Probability (PDP) of Single-Photon Avalanche Diodes (SPAD). The efficiency of the proposed simulation flow is demonstrated through a complete study aimed at improving the PDP of a SPAD implemented in 28nm Fully Depleted Silicon-On-Insulator (FD-SOI) CMOS technology using a light-trapping approach (thanks to the patterning of Shallow Trench Insolation – STI layer). Simulation shows an increase of PDP spectrum of over 50% at wavelengths of 400-550nm and 750-1000nm and of 10-15% at the wavelengths of 550750nm, compared to a reference SPAD without any nanostructuration.