Optimum Sizing Strategy of Starving resistor in Buffer for Short Circuit Loss Minimization

This paper investigated the optimum sizing strategy of a starving resistor in a pre-driver/buffer scheme. The starving resistor is helpful in short through loss reduction of a buffer. Inside a buffer, the NMOS and PMOS of the penultimate stage inverter are driven by different time-skewed signals employing a starving resistor. The optimum size of the starving MOS w.r.t inverter's MOS is nearly fixed for standard processes. The value seven and eight have emerged as the optimum ratio in 0.35 mu m and 0.18 mu m processes for a standalone buffer unit. We implemented a buck converter utilizing this buffer in both 0.35 mu m and 0.18 mu m processes. The optimum ratio has not changed much during full-scale converter implementation. SPICE simulations and mathematical analysis validate the claim.