A 3.3v 14-Bit 10msps Calibration-Free Cmos Pipelined A/D Converter

A calibration-free 3.3V 14-bit 10 MSPS pipelined analog-to-digital(A/D) converter was implemented using a 0.35 um CMOS technology. The ADC utilize a I-stage pipelined architecture with a wide-band sample and hold amplifier and achieves the highest resolution reported to date at 3.3V 10MHz The proposed hybrid capacitor switching technique of one/two feedback capacitors is applied to improve the linearity which is limited by component mismatch depending on the process. Since the proposed technique can be implemented by simple circuit compared I with previous self-calibration techniques, it allows smaller area and lower power consumption.The A/D converter occupies a die area of 2.43 mm(2) (1800um*1350um) and dissipates 118 mW at a 10 MHz clock rare with a 3.3V single supply voltage in measurement result. Typical differential nonlinearity (DNL) and integral nonlinearity(INL) are +/-0.73 LSB and +/-1.55 LSB, respectively.