Failure Mechanism Of Integrated Circuits Investigated Experimentally And Theoretically Under Electrical Fast Transient

The Electrical Fast Transient (EFT) interference may affect the performance of the device or even cause the device failure. To study the anti-EFT interference performance of integrated circuit (IC), an EFT test platform of a SoC MCU chip has been set up. And the power pin of MCU integrated circuit shows better anti-interference performance than that of interface pin. Since I/O failure is mainly caused by MOSFET failure in clamp circuit, OBIRCH, SEM and other means are used to locate the failure position and accurately analyze the failure points. And the failure mechanism of the MOSFET in the I/O circuit has been analyzed according to the observation results. The MOSFET in the I/O circuit is fused under the positive feedback effect of the decrease of resistivity and the increase of current density, which leads to the I/O failure. The failure mechanism of MOSFET under high speed pulse is also verified by simulation. The results show that the only hot spot, firstly reaching the silicon melting point due to heat deposition originating from Electromagnetic Pulse (EMP) injection, is at the drain-substrate PN junction. The device fails or burns out with thermally damages due to electrical heating coupling.