Characterizing the On-chip Temperature of an Off-the-shelf TSV-based 3D Stacked CPU

Three-dimensional (3D) integration is adopted in the semiconductor industry to overcome the slowdown of Moore's Law. The 3D integration is beneficial in terms of interconnection bandwidth, wire delay, power efficiency, and area. However, the on-chip temperature of 3D stacked CPUs is known as much higher than that of conventional 2D CPUs due to the higher power density and lower heat dissipation capability. High on-chip temperature leads to performance degradation of 3D stacked CPUs due to following reasons: 1) High on-chip temperature leads to frequent Dynamic Thermal Management (DTM) invocations, which limits practical CPU voltage and clock frequency. 2) The power limits are used to proactively deal with the thermal problems from high on-chip temperature by adjusting the CPU clock frequency. In this paper, we explore the thermal characteristics of the first off-the-shelf through-silicon-via (TSV) based 3D stacked CPU (Intel Lakefield). In our evaluation, 3D CPU w/ the forced air cooling w/o PL1 shows 21.7% and 6% better single thread performance, on average, compared to 3D CPU w/ PL1 and 3D CPU w/o PL1, respectively. Although the 3D stacked CPU was launched to the market, we identify that the thermal problems of the 3D stacked CPU have not been fully resolved. To tackle the thermal problems of 3D stacked CPUs in the future, researchers are required to consider more innovative integration technologies, optimized DTM techniques, and advanced cooling solutions.