Exploring The Effect Of Segmentation On A 10-Bit Dac

This paper investigates the impact of segmentation on the DNL (differential non-linearity) and INL (integral non-linearity) of a 10-bit differential output current-steering digital-to-analog converter (DAC), implemented in a 40 nm, 2.5 V, CMOS process. The achievable DNL improvement was characterized by simulating all intermediate degrees of segmentation possible between a binary and a thermometer implementation. The DNL results ranged between (-0.467, +0.474) LSB and (-0.024, +0.026) LSB with the INL remaining almost invariant at (-0.376, +0.345) LSB. A differential output current of +/-1mA was achieved for a circuit with an active analog area of 0.01 mm(2). All decoder variants required for driving the analog content of the DAC have been physically implemented with their area documented. The theoretical results for the DNL and INL are compared with the Monte Carlo simulation results and are shown to be within a 30% margin of error.