F-band Frequency Multipliers with Fundamental and Harmonic Rejection for Improved Conversion Gain and Output Power

This paper introduces several design techniques to improve the performance of CMOS frequency multipliers that operate at the sub-THz band without increasing the complexity and the power consumption of the circuit. The proposed techniques are applied to a device nonlinearity-based frequency tripler and to a push-push frequency doubler. By utilizing the fundamental and second harmonic feedback cancellation, the tripler achieves -2.9 dBm output power with a simple single-ended circuit architecture reducing the required area and power consumption. The tripler operates at frequencies from 103 GHz to 130 GHz. The introduced modified push-push doubler provides 2.3 dB conversion gain including the balun losses and it has good tolerance against balun mismatches. The output frequency of the doubler is from 118 GHz to 124 GHz. Both circuits were designed and fabricated using CMOS 65 nm technology.