Unified integer and carry-less modular multiplier and a reduction circuit

Suresh Vikram B,Mathew Sanu K,Satpathy Sudhir K,Gopal Vinodh,VB Suresh,SK Mathew,SK Satpathy,V Gopal

user-618b9067e554220b8f259598（2019）

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摘要

In one embodiment, a processor comprises a multiplier circuit to operate in an integer multiplication mode responsive to a first value of a configuration parameter; and operate in a carry-less multiplication mode responsive to a second value of the configuration parameter.

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关键词

Analog multiplier,Multiplication,Integer (computer science),Reduction (complexity),Value (computer science),Carry (arithmetic),Topology,Mode (statistics),Computer science,Modular multiplier

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