Chiplet/Interposer Co-Design for Power Delivery Network Optimization in Heterogeneous 2.5-D ICs

In this article, we present an effective methodology for co-design, co-analysis, and the system-level optimization of chiplet/interposer power delivery network (PDN) in 2.5-D integrated chip (IC) designs. In our methodology, we first generate a commercial-grade heterogeneous 2.5-D IC designs including full signal routing and power delivery. We then perform our PDN co-analysis in frequency and time...