A 112-Gb/s PAM-4 Low-Power Nine-Tap Sliding-Block DFE in a 7-nm FinFET Wireline Receiver

Practical realization of decision feedback equalizers (DFEs) has to date been limited to at most two taps in 100-Gb/s long-reach (LR) wireline applications due to significant power, area, and timing costs. This article presents a systolic many-tap low-complexity sliding-block decision feedback equalizer (SB-DFE) that overcomes the implementation challenges of conventional DFEs with no performance ...