OpenFPGA: Towards Automated Prototyping for Versatile FPGAs

This paper introduces an open-source framework OpenFPGA which aims to automate the design, verification and layout of highly versatile FPGA architectures. OpenFPGA offers a high-level architecture description language for users to customize their FPGA architectures down to circuit-level details. Based on the architecture modeling, OpenFPGA can auto-generate Verilog netlists, with which users can perform verification as well as generate production-ready layouts using modern EDA tools. OpenFPGA includes a generic Verilog-toBitstream generator, as a native EDA toolchain for any FPGAs that are prototyped by OpenFPGA. To demonstrate the capability of OpenFPGA, we showcase the <24-hour layout generation of two FPGA fabrics which are based on Stratix-like architecture built with a commercial 12nm standard-cell library and 40nm custom cells respectively.