A High Reliable SRAM-Based PUF With Enhanced Challenge-Response Space

This brief proposes a sequence-dependent SRAM-based PUF with enhanced reliability. It expands the CPRs by order of (rows $^{(sequence\,\,length\,\,}{}^{+}{}^{\,\,}{}^{2}{}^{)}\,\, \mathbf {\mathrm {\times }}$ columns) for reliable authentication. The proposed bitcell utilizes split word-lines to control two access transistors separately. The PUF mode turns on two left word-lines and two right word-lines simultaneously, including 18 transistors for generating one-bit data. This proposed technique supports rendering multiple data maps from one chip. Besides, various temperature and voltage combinations can create a reliability map for each data map. A test chip was fabricated in 40 nm CMOS technology. The measured worst bit error rate is 0.8% at the nominal point (1V, $20 \mathbf {\mathrm {^\circ }}$ C). From a single chip, the proposed PUF achieved the hamming distances of 41.29% for one sequence with different orders and 44.93% for other sequences, respectively. The measured inter-chip hamming distance is 49.64%.