A Multilayer Perceptron Training Accelerator using Systolic Array

Neural networks are now used in various applications, and the demand for fast training with large amounts of data is emerging. For example, a network intrusion detection (NID) system needs to be trained in a short period to detect attacks based on large amount of traffic logs. We propose a training accelerator as a systolic array on a Xilinx U50 Alveo FPGA card to solve this problem. We found that the accuracy is almost the same as conventional training even when the forward and backward paths are run simultaneously by delaying the weight update. Compared to the Intel Core i9 CPU and NVIDIA RTX 3090 GPU, it was three times faster than the CPU and 2.5 times faster than the GPU. The processing speed per power consumption was 11.5 times better than the CPU and 21.4 times better than the GPU. From these results, we can conclude that implementing a training accelerator on FPGAs as a systolic array can achieve high speed and high energy efficiency.