Performance Improvement of Charge‐trap Memory by Using a Stacked Zr0.46Si0.54O2/Al2O3 Charge‐trapping Layer

The postdeposition annealing (PDA)‐treated charge‐trap flash memory capacitor with stacked Zr0.46Si0.54O2/Al2O3 charge‐trapping layer flanked by a SiO2 tunneling oxide and an Al2O3 blocking oxide was fabricated and investigated. It is observed that the memory capacitor exhibits prominent memory characteristics with large memory windows 12.8 V in a ±10 V gate sweeping voltage range, faster program/erase speed, and good data‐retention characteristics even at 125 °C compared to a single charge‐trapping layer (Zr0.46Si0.54O2, Zr0.79Si0.21O2, and Zr0.46Al1.08O2.54). The quantum wells and introduced interfacial traps of the stacked trapping layer regulate the storage and loss behavior of charges, and jointly contribute to the improved memory characteristics. Hence, the memory capacitor with a stacked trapping layer is a promising candidate in future nonvolatile charge‐trap memory device design and application.