Hdl Based Design Problems For Computer Architecture

NOTE: The first page of text has been automatically extracted and included below in lieu of an abstract HDL Based Design Problems For Computer Architecture Abstract A computer architecture course is a necessary component in a computer engineering curriculum. Students in related disciplines such as electrical engineering and computer science may also value course concepts in the development of their elective coursework. There are many excellent computer architecture textbooks available to illuminate the difficult concepts encountered within the topic area. Many contain detailed designs of various architectures and configurations. To enhance the design skills and allow students to observe the dynamic operation of specific computer architectures, a series of Verilog Hardware Descriptive Language (HDL) design exercises were developed for a senior/graduate level course in computer architecture. The exercises allowed students to begin with basic review exercises on HDL design techniques and progress to fully operational computer architectures. The exercises were directly based and coupled with architectures presented in the course textbook by Mano and Kime. Student feedback indicated the exercises significantly enhanced their design skills and their overall understanding of computer architecture concepts. Students also demonstrated the capability to analyze more complex computer architectures and synthesize advanced components of a computer architecture and apply their knowledge to challenging open-ended design projects. Although originally developed for the Mano and Kime textbook, the design exercises described may be used with any computer architecture text. Overview There are many tools used in the design of microprocessors and microcontrollers to increase their speed and performance: manufacturing/processing, software development, and computer architecture. Previous advances in computer architecture were made possible by the reduction of the transistor size and performance and enhancement in architecture design. More recent computer architecture enhancements have focused on multiple cores and parallel processing in design. It is essential that computer architecture students understand the fundamental concepts as well as advanced techniques [1]. Computer architectures have evolved over many years and today there are many different types of computer architectures. Some are made for the general user, while others focus on a specific application. To help develop these architectures, engineers often use a Hardware Descriptive Language (HDL). In some cases, the HDL models can be compiled and implemented into field-programmable gate arrays FPGAs for further testing or even mask layouts for final or near-final production. Each processor manufacturer has its own specific procedures to move a design to the production phase. This being said, HDL based designs are clearly advantageous in academics, implying a need for homework based on HDL. This paper describes a series of homework assignments that have been recently developed to enhance the instruction of complex computer architectures using Verilog HDL as a design vehicle. The organization of these homework assignments attempts to show students the link between