An Energy Efficient Carry-Free Inner Product Unit

An energy efficient truncated inner product unit is proposed in this paper. The proposed unit is pipelined and processes the $m$ pairs of n-bit operands in serial, so that only one unit is required and it can be reused in each recurrence. Truncated inner product is produced so that no accumulation is needed for the lower part. The array reduction unit is bit-level pipelined to improve throughput and reduce the initial delay. A two-level [4:2] adder is proposed to accumulate redundant vectors with non-uniform input arrival. The proposed inner product is compared with other truncated inner product units using fully merged arithmetic, partially merged arithmetic and the counter based inner product for different precision and vector length. Our proposed inner product unit has significant reduction in area, power and energy.