A Study on the Yield Loss Due to Al(Cu) Interconnections with Spacing Failure

Abstract This paper presents the results of a study on yield loss in wafers produced using a 0.25-μm CMOS process. It describes how the authors determined that a short in the M1 metal layer was the major yield killer and how they traced the cause to excess Cu that they believe migrated to the bottom of the Al(Cu)/TiN interface, forming θ-phase Al2Cu precipitates known to interfere with metal etching processes. It explains how TiN bridges, the result of incomplete etching, were observed between adjacent metal lines in failed die, confirming the authors’ theory and shedding light on potential solutions to the yield problem.