Enhancing Multi-level Cache Performance Using Dynamic R-F Characteristics

Cache memory or CPU memory is a high-speed static random access memory that a computer microprocessor can access more quickly than it can access regular random access memory. Hence, the high-performance cache memory is used to bridge the performance gap between the processor and main memory. Multi-level caches refer to a type of memory hierarchy which uses memory stores with different access speed to cache data. Our proposed work uses combination of different tuning algorithms considering the R-F characteristics of page to provide an efficient solution for cache replacement in multi-level cache hierarchy which has an easy implementation and a better performance compared to traditional cache replacement policies like clock with adaptive replacement (CAR), least recently used (LRU), and first in, first out (FIFO) on a cache of equivalent size.