A 55.9-fs Integrated Jitter (100 kHz–100 MHz) Hybrid LC-Tank PLL in 5-nm FinFET Using Programmable Phase Realignment and Dynamic Coarse Tuning

IEEE Solid-State Circuits Letters(2021)

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摘要
We propose a hybrid LC-tank PLL realized in 5-nm FinFET CMOS for radar and 5G mobile applications. The oscillator has three input ports: 1) a conventional arrangement of phase/frequency detector and charge pump controls the oscillator via its tuning voltage; 2) a programmable phase realignment injects ultranarrow and ultrasharp complementary reference pulses into the oscillator to adjust the timing of its waveform’s peaks and valleys; this improves the in-band phase noise and helps to mitigate the worsening flicker noise in advanced process nodes; and 3) a dynamic coarse tuning digitally extends the oscillator’s tracking range by allowing it to quickly recenter the varactor. The PLL achieves 55.9-fs integrated jitter (from 100 kHz to 100 MHz).
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关键词
Dynamic coarse tuning (DCT),fast settling,hybrid PLL,injection locking,realignment,reference spur
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