Design and Verification of Radiation Hardened Scanning D Flip-Flop

Radiation is one of the main challenges in the design of nanoscale integrated circuits in aerospace equipment. Aerospace chips need to be designed based on standard cell libraries that are radiation resistant. The design for testability (DFT) based on a specific cell library is a technique to enhance reliability in the chip design process, and the scanning D flip-flop is the indispensable unit required for testability design. This paper focuses on the DFT of the radiation resistant chip. Aiming at the problem of no scanning D flip-flops in the radiation resistant standard cell library of SMIC 0.18um, the radiation hardened scan D flip-flops are designed and verified from the circuit and layout levels. The simulation results show that the radiation hardened scanning D flip-flop has a reliable radiation resistant ability under the premise of ensuring the correct function. Then, by embedding our designed 30 scanning D flip-flops to the SMIC 0.18um standard cell library, the further evaluation shows that the designed scanning D flip-flops can realize the testability design requirements of the radiation resistant SoC chip.