A Survey on Placement and Routing for Field-Coupled Nanocomputing

CMOS technology is reaching power, thermal, and physical limits at an alarming pace. As a response, post-silicon research investigates alternative technologies to perform computation. Field-Coupled Nanocomputing (FCN) presents low power dissipation, high frequencies, and room temperature operation. Nevertheless, FCN imposes several challenges in the development of efficient and scalable CAD tools. The placement and routing step is especially tricky in FCN compared to CMOS because of synchronization issues inherent to these technologies, such as path balancing and reconvergent paths. In this work, we survey the state-of-art of placement and routing algorithms for FCN. We describe the most recent FCN placement and routing algorithms, highlighting their limitations and, finally, presenting future work directions.