Fast Combinational Architecture for a Vedic Divider

This paper proposes a fast, purely combinational implementation of a divider, based on the Dhwajanka Sutra of Vedic mathematics. Vedic mathematics offers algorithms that are computationally efficient over conventional arithmetic algorithms. Dhwajanka Sutra has been chosen as it is an algorithm efficient for all possible cases, unlike other sutras for division (Nikhilam and Paravartya) which are case specific. The simplicity of the Vedic algorithm implemented in combinational form has reduced computation time significantly The proposed design is compared with existing divider architectures implemented on an FPGA namely Non-restoring Algorithm based Divider, Vedic Divider (Paravartya Algorithm), Vedic Divider (Nikhilam Algorithm), Decimal Divider based on Newton Raphson algorithm, Decimal Divider based on SRT algorithm and Combination divider algorithms. The proposed vedic divider shows a maximum of 273.72% speed improvement while the minimum is 99.95%. The results have been validated using the Xilinx ISE Design Suite 14.7, on the Virtex5 (xc5vlx20T-2ff323) FPGA Target Technology and the design has been implemented in Verilog.