The charge islands SOI LDMOS with back-side etching technology

The charge islands SOI LDMOS with Back-side Etching technology structure is proposed. The new structure features the equally spaced charge islands of the upper LDMOS and a back-side etched structure of the lower LDMOS. A series of equidistant high concentration N+ regions are formed at the upper SOI LDMOS by the ion implanting method. The breakdown voltage of the device is improved due to dielectric field enhancement and the interaction of charges. The results show that the breakdown voltage is increased from 210V to 615V (192.8% enhanced), compared to the conventional LDMOS. The on-resistance of the as-studied stacked SOI LDMOS reduces from 48.2 Ω⋅mm2 to 37.23 Ω⋅mm2 comparing with conventional charge islands device, leading to a reduction ratio of 22.7%.