A Tanner Based Approach to analyse the comparisons between 6T and 8T SRAM

The WRITE phase for a Complementary Metal Oxide Semiconductor (CMOS) Static Random-Access Memory (SRAM) cell was investigated. We've focused in particular on a phenomenon known as dynamic power dissipation. This occurrence occurs in the CMOS SRAM cell during the WRITE operation. During the Write 0 and Write 1 operations, we discovered that the discharging and charging of bit lines consumes greater power while the CMOS SRAM call is active. In the pull-down route of an 8T SRAM cell, two additional trail transistors are required for correct discharging and charging of the bit lines. The results are mostly taken into account based on various frequencies that have been set. For the circuit analysis, we employed 130 nm technology and a supply voltage of 1.5 V. We were able to lower the dissipated power of the low-power 8T SRAM cell by comparing the results to previous work, which was done with a 6T SRAM cell.