A Near-array Convolution Computing Scheme Based on WSe₂ Photodiode

Due to the separation of perception and computing, the movement of data between perception devices and computing devices has become a bottleneck in intelligent systems. In that case, In-Sensor Computing (ISC) systems bring favorable opportunities for power-limited recognition devices. It integrates perception and computation, shortening the moving path of data, and therefore reducing energy consumption. However, the conventional schemes are still suffering from the issues of either low fill factor or low computing efficiency. Recently, a novel photodiode is developed using WSe2 material, whose photoresponsivity can be controlled by the gate voltage. In this paper, an efficient ISC scheme is proposed for convolution operation to take full advantage of the above photodiode. In our scheme, the kernel weights can be stored in a continuously tunable photoresponsivity matrix. The proposed ISC scheme can realize flexible-sized kernel-readout with minimum one step for convolutional operations. A simulation is conducted on a 7 * 7 pixel array, with specifically filter size of 3 * 3, strides of 2, and padding of 0 (the realization of other array sizes and filter sizes will also be discussed). Meanwhile, the architecture is optimized to enable parallel convolution operation. The multiplication is achieved during the exposure period by preset the photoresponsivity matrix. The results show that the proposed ISC can achieve up to 20.6 TOPS/W energy efficiency with 9.71 pJ/pixel/frame power consumption and a maximum processing speed of 20 MHz, and the fill factor is 97%, outperforming the state-of-the-art.