High-Throughput Low-Latency Pipelined Divider for Single-Precision Floating-Point Numbers

IEEE Transactions on Very Large Scale Integration (VLSI) Systems(2022)

引用 1|浏览23
暂无评分
摘要
In this brief, we propose a fully pipelined divider for single-precision floating-point numbers based on a universal piecewise linear (PWL) approximation method and a modified Goldschmidt algorithm. The state-of-the-art universal PWL method uses a suitable number of segments and fractional bit widths to meet the requirement of the predefined maximum absolute error. Small multipliers are employed i...
更多
查看译文
关键词
Approximation algorithms,Hardware,Encoding,Very large scale integration,Adders,Throughput,Periodic structures
AI 理解论文
溯源树
样例
生成溯源树,研究论文发展脉络
Chat Paper
正在生成论文摘要