TEA-Z: A Tiny and Efficient Architecture Based on Z Channel for Image Watermarking and Its Versatile Hardware Implementation

With the popularity of smart phones and digital cameras, authentication and protection of digital images have become important to every producer and consumer. Although many digital watermarking methods have been proposed to mitigate the growing problem of online piracy, their efficient deployment for real-time processing in hardware lacks sufficient attention. Hence, with the first introduction of ${Z}$ channel, this article advances a tiny and efficient architecture named TEA-Z to implement digital watermarking for color images. Avoiding complex computing units with the general color space conversion (GCSC) and simplified discrete cosine transform (DCT), TEA-Z can better achieve the design goals of low complexity, high efficiency, and easy deployment compared with the latest methods. For FPGA implementation, TEA-Z can achieve the maximum frame rate of 3150 frames/s for 256 $\times $ 256 color images and peak energy efficiency of 4.13 $\times \,\,\textbf {10}^{\textbf {5}}$ Mbps/W at the maximum frequency of 206.48 MHz. For ASIC implementation, the peak energy efficiency will be 2.40 $\times \,\,\textbf {10}^{\textbf {7}}$ Mbps/W with the tiny area of 0.00356 $\textbf {mm}^{\textbf {2}}$ and ultralow power of 0.2002 mW at the frequency of 200 MHz under 90-nm CMOS technology. Moreover, TEA-Z can provide various watermarking strategies with its configurations to meet different needs.