A 1000fps High SNR Voltage-domain Global Shutter CMOS Image Sensor with Two-stage LOFIC for In-Situ Fluid Concentration Distribution Measurements

This paper presents a prototype global shutter CMOS image sensor (CIS) with high signal-to-noise ratio (SNR) and 1000 fps performances for in-situ fluid concentration distribution measurements. The developed 22.4 μm pitch pixel consists of a high UVlight robustness UV-visible-NIR waveband pinned photodiode (PD), two-stage lateral overflow integration capacitor (LOFIC) for wide dynamic range and high SNR and voltage-domain memory bank for global shutter (GS), both formed by high density Si trench capacitors. The developed CIS exhibited 69.8 dB maximum SNR, 123 dB dynamic range and 1000 fps maximum frame rate, and successfully captured images of dynamic movement of NO2 gas concentration distribution in the vacuum chamber. INTRODUCTION Practical realization of smart manufacturing, agriculture and healthcare are critical to improve the productivity and sustainability of our society. In these fields, next generation IoT technologies are needed that can visualize concentration distribution of dynamically moving gases and liquids by noninvasive/non-destructive manners. For example, realtime visualization of gas concentration distribution inside process chamber of semiconductor manufacturing equipment would greatly improve process condition optimization as well as process diagnosis. Several concentration measurement methods using light absorption have been utilized in high performance liquid chromatography with linear array sensor, gas concentration sensor with a single photodiode and so on. As in the equation below, the use of a strong light source and a sensor with a high full well capacity (FWC) can improve the SNR and enable high-precision measurements, SNR = 20 log10 ( Nsig √√Nsig 2 + nsys 2 ) ≅ 20 log10√Nsig (1) where, Nsig is the number of signal electrons and nsys is the input referred number of system noise electrons. In conventional methods with linear array sensors or single point detectors, high FWC has been achieved by using a large PD or attaching a large capacitor to the PD. In order to acquire concentration distribution information with high accuracy by the absorption imaging, an image sensor with extremely high FWC pixels need to be developed. For instance, in order to achieve 70 dB SNR, an over 10Me FWC is needed. There are several technologies to increase FWC in CMOS image sensors, such as stacking organic photoconductive film on reading circuit, complementary carrier collection and lateral over flow integration capacitor (LOFIC) and so on. By using LOFIC, PD, FD and LOFIC can be optimized independently and due to its linear response it is suitable for high precision absorption imaging. In addition to SNR, there are other requirements for absorption imaging. First, high speed and GS operation is desirable to capture fast-moving objects without distortion, such as gases in the semiconductor process chamber. When measuring the concentration of individual substances in a mixture gases or liquids, it is necessary to switch the light source with the appropriate wavelengths. Here the GS is advantageous to efficiently synchronize the exposure period and the light illumination timing. Thanks to the high density capacitor technologies reported resent years, the noise performance of the voltage-domain GS CIS has been improved. Next, a wide spectral response covering UV, visible to NIR is also required to capture the light absorption of various materials. A CIS for UV/visible/NIR absorption imaging that satisfies all of these requirements simultaneously has not yet been reported so far. This paper presents a high-speed and high SNR voltage-domain global shutter CIS with two-stage LOFIC toward in-situ fluid concentration distribution measurements using absorption imaging. DESIGN AND STRUCTURE OF DEVELOPED CMOS IMAGE SENSEOR Figs. 1 and 2 show the pixel layout and circuit diagrams of the developed CIS and pixel cross-section, respectively. It consists of a high UV-light robustness UV-visible-NIR waveband pinned PD with high concentration p layer with steep dopant profile, twostage LOFIC and voltage-domain memory bank with six S/H capacitors. High density Si trench capacitors were employed for LOFIC1 (71.4 fF), LOFIC2 (2.59 pF) and the memory bank (214.2 fF each) that consist of 1, 37 and 3 units of capacitor cells, respectively. Here the LOFIC capacitance values were designed to achieve 70 dB maximum SNR and approximately 30 dB SNR at the signal switching points. Also, the capacitance of the memory bank was designed to sufficiently reduce thermal noise. These trench capacitors were surrounded by a deep p-well to prevent a leakage between the PD and the inversion layer of trench capacitors. The highly reliable SiO2 dielectric was employed to achieve low leakage. In addition, symmetrical and periodic arrangement of the capacitors reduces variation in optical and electrical characteristics. Recently a GS CIS for soft X-ray detector with two-stage LOFIC and memory bank was reported to be useful for wide dynamic range soft X-ray imaging. The gate sizes of the drive transistors for SF1 and SF2 and as well asl the current sources were designed to enable 1000 fps operation. Fig. 3 shows the circuit block diagram of developed CIS. It consists of pixel array, analog memory for pixel output, vertical and horizontal shift registers for signal readout and output buffers. The three differential pairs of high sensitivity, high saturation and the highest saturation signals are readout. The multiplexer switches between the GS operation mode and the rowby-row readout operation mode by ΦRead. The HSR operates at 40 MHz for 1000 fps operation. Fig. 4 shows the potential diagram and Figs. 5 and 6 show the GS and readout operation timing diagrams, respectively. In the GS operation, ΦREAD is set to low. Under a high illumination condition, photoelectrons overflown from the PD are accumulated in LOFIC1 and 2 (t1). A reference signal for the high sensitivity S1 signal is readout by SF1 and stored in N1 memory (t2). Photoelectrons in the PD are transferred to FD (t3). A high sensitivity S1 signal is readout at FD (t4), a high saturation S2 signal is readout at FD + LOFIC1 (t5) and the highest S3 signal is read out at FD + LOFIC1 + LOFIC2 (t6) and they are stored in the S1, S2 and S3 memories respectively. Then, PD are reset by R1 and reset signal for S3 is read out at FD + LOFIC1 + LOFIC2 (t7) and reset signal for S2 is read out at FD + LOFIC1 (t8) and they are stored in the N3 and N2 memories respectively. After all signals are readout, ΦREAD switches to high, and the readout operation and the integration time for the next frame start. The signal of the row selected by the VSR is output to the column analog memories via the vertical signal line, and readout by the HSR to the horizontal signal line sequentially. Fig. 7 shows the micrograph of the developed chip. The developed CIS was fabricated using a 0.18 μm 1poly-Si 5-Metal CMOS image sensor process technology with pinned PD. The power supply voltage is 3.3 V and the die size is 4.8 mm×4.8 mm. The pixel size and the number of the effective pixels are 22.4 μm×22.4 μm and 140×140, respectively. Fig. 1 Pixel layout and circuit diagrams of the developed CIS. Fig. 3 Circuit block diagram. Fig. 4 Potential diagrams of two-stage LOFIC under high illumination. Fig. 5 Global shutter operation timing diagram. Fig. 2 Pixel cross section. t1 t2 t3 t4 t6 t5 t7