A 40/22nm 200MP Stacked CMOS Image Sensor with 0.61μm Pixel

Abstract―We developed a new 40/22nm stacked 200 mega-pixel CMOS image sensor (CIS) with a 0.61μm pixel. By using a 22nm logic wafer process node instead of 40nm, digital power consumption was reduced by half while keeping the same clock frequency, and the full high definition (FHD) frame rate was increased from 240fps to 480fps. In this work, we demonstrate a new source follower (SF) transistor architecture with 63% higher SF transconductance (Gm) compared with our former 0.7μm pixel. A full well capacity (FWC) of 5.0kewas achieved without lag or blooming, with better white pixel (WP) performance compared to the 0.7μm pixel. We demonstrate a 0.61μm quad photodiode (QPD) structure capable of achieving comparable quantum efficiency (QE) performance to 0.7μm QPD in the visible light range.