High-speed Clock and Data Recovery System with Segmented Slew-rate Control Circuit for High-linearity in 65 nm CMOS Process

A phase interpolator (PI) based all-digital clock and data recovery (CDR) system has been fabricated in 65 nm CMOS process. The segmented switching units control the slew rate of input clock signal in the PI and the linearity of PI control code and output phase shift steps is improved by 0.4 LSB for standard deviation of differential nonlinearity (DNL). The measurement results show that our CDR locks successfully for 6 Gbit/s non-return to zero (NRZ) high-speed signal with 2(32)-1 pseudo-random bit sequence (PRBS) pattern. The input NRZ input signal has 2.05 ps of root-mean square (RMS) jitter and 1 V-dpp of swing. When the loop is locked, the output clock signal shows 12.2 ps of peak-to-peak jitter and 1.826 ps of RMS jitter, which is divide 16 speed of the full rate. The measured phase noise of the recovered clock is -114.72 dBc/Hz at 1 MHz offset. The designed built-in pattern checker in receiver exhibits 10(-12) of bit error rate (BER) at the center of data eye. The lock time of the loop measured via 7-bit monitoring digital-to-analog converter (DAC) is 54.5 ns. The prototype CDR occupies 0.073 mm(2) chip area and consumes 17.4 mW from 1.0 V power supply.