3D TSV hybrid pixel detector modules with ATLAS FE-I4 readout electronic chip

The through silicon via (TSV) technology has been introduced in a wide range of electronic packaging applications. Hybrid pixel detectors for X-ray imaging and for high-energy physics (HEP) can benefit from this technology as well. A 3D TSV prototype using the ATLAS FE-I4 readout electronic chip is described in this paper. This type of readout chip is already prepared for the TSV backside process providing a TSV landing pad in the first metal layer of the backend-of-line (BEOL) layer stack. Based on this precondition a TSV backside via-last process is developed on ATLAS FE-I4 readout chip wafer. The readout chip wafers were thinned to 100 mu m and 80 mu m final thickness and straight sidewall vias with 60 mu m in diameter has been etched into the silicon from wafer backside using deep reactive ion etching (DRIE). The filling of the TSVs and the formation of the wafer backside interconnection were provided by a copper electroplating process. ATLAS FE-I4 readout chips with through silicon vias has been successfully tested, tuned and operated. In addition, hybrid pixel detector modules have been flip chip bonded using ATLAS FE-I4 TSV readout chips and planar sensor chips. After mounting the bare modules onto a support PCB, its full functionality has been verified with a source scan.