A 2.4-GHz Sub-Sampling PLL With an Adaptive and No Power Contribution FLL Achieving 103.58 fs rms Jitter and −257.8 dB FOM

IEEE Microwave and Wireless Components Letters(2022)

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摘要
A sub-sampling PLL (SSPLL) employing an adaptive frequency-locked loop (FLL) without static power consumption is proposed in this letter. A new unlock detection mechanism and a configurable PFD are realized in the adaptive FLL. With the new unlock detection mechanism, while the FLL that contains phase detector, divider, and charge pump dissipates no power during the locked steady state, it automat...
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关键词
Frequency locked loops,Phase locked loops,Voltage-controlled oscillators,Phase frequency detectors,Time-frequency analysis,Jitter,Delays
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