Influence of phosphorus diffusion on the SiO2/4H-SiC (0001) interface during poly gate formation process

The work confirms the flat-band voltage (VFB) and SiC/SiO2 interface state density (Dit) characteristics 4H-of the SiC MOS capacitors, the oxide was obtained by performing a conventional thermal dry oxidation process on a 4H-SiC Si-face (0001) epi-wafer followed by Ar post-oxidation-annealing (POA). Poly gate and Al gate capacitors are formed on the same wafer and phosphorus is implanted into polysilicon to form the poly gate electrode. We found that the positive VFB shift is remarkable in the Al gate sample, the △VFB is about 1.4 V, but the shift is well suppressed in the Poly gate sample(△VFB ≈ −0.05 V), which suggests that the poly gate process reduce the instability of VFB. To some extent P diffusion from the Poly gate process plays an important role in compensating the charge trapping sites. The Dit of the Poly gate sample is also shown to be lower than the Al gate sample, particularly in the area of Ec-E > 0.4 eV. In addition, we confirmed that the Dit has a temperature dependence and thus is electrically active at elevated temperatures. Finally, secondary ion mass spectrometry (SIMS) measurements were carried out to investigate the differences between the Poly gate and Al gate samples. The results imply that there is a correlation between the increase in the phosphorus density at the interface and the observed reduction in Dit.