A Timing Fault Model and an Efficient Timing Fault Simulation Method for Rapid Single-Flux-Quantum Logic Circuits

We examine digital behavior of faults caused by a change of the order of the pulse arrivals in Rapid Single-Flux-Quantum (RSFQ) logic circuits. Based on the timing fault model, we present a flow of automatic test pattern generation for testing digital RSFQ chips. As the test pattern generation repeatedly executes fault simulation, the scalability depends on computational cost of the simulation. We propose an efficient fault simulation method based on two ideas. First, we share computation for the fault-free circuit and faulty circuits as much as possible. Secondly, we exploit the pipelined behavior of RSFQ logic circuits to suppress computation for unnecessary signals. We have implemented our simulation method and obtained evaluation results to show that our method is effective for large circuits.