Reconfigurable Hardware Design of Multi-lanes Number Theoretic Transform for Lattice-based Cryptography

The performance of number theoretic transformation in lattice-based cryptography is insufficient, andthe number theoretic transformation parameters are different. A Random Access Memory (RAM)-basedreconfigurable multi-lanes number theoretic transform is proposed. In the design of number theorytransformation unit, the multi-lanes architecture is improved on the time decimation operation architecture,and an optimized address allocation method is proposed. The number theory transform unit is implemented onXilinx artix-7 Field Programmable Gate Array (FPGA) platform. The results show that the resource consumedby the unit is 1744 slices and 16 DSP, and the time to complete a polynomial multiplication is 2.01 ms (n=256),3.57 ms (n=512), 6.71 ms (n=1024) and 13.43 ms (n=2048). The unit supports reconfigurable configurations of 256 similar to 2048 parameters n and 13 similar to 32-bit modulus q, and the maximum operating frequency is 232 MHz