A Ka-band 7-bit Digital Attenuator with Temperature Compensation Technique in 40nm CMOS

A Ka-band 7-bit CMOS digital step attenuator with low temperature error is presented. The digital attenuator was implemented using a 40nm CMOS process. It has a maximum attenuation range of 31.5dB with 0.5dB steps. With the temperature compensation technique, the digital attenuator exhibits the root-mean-square (RMS) amplitude error less than 0.33dB and a RMS relative phase error less than 4.8°over 27.531 GHz in a large temperature range. The insertion loss is 7.8-8.2dB and the 1-dB compression point is 15.35dBm at 29.5GHz under 27°C. The core chip size is 0.52×0.86 mm ² .