Efficient Tree Multiplier Design by using Modulo 2ⁿ + 1 Adder

Residue Number System is a carry-free system used in various applications of high speed arithmetic component like digital signal processing, image processing and cryptography. The main work of RNS is to reduce the complexity and to perform operations on overflow detection, sign detection and magnitude comparison. In this paper, we propose the parallel architecture based on parallel prefix tree is helpful for computation at higher speed. This work is carried out to get a regular binary multiplication technique, basically consists of modulo reduction operation. Conversion has been done between binary and diminished-1 representation for a large value of inputs. Proposed work with parallel prefix tree adder improves the speed of multiplication. This modified parallel prefix adder consumes less area as compared to Kogge Stone adder. The proposed work is consisting of a carry-computation unit depends on the carry-generate and carry-propagate terms. In this paper, the area of carry computation unit of modulo adder has been reduced. Then, the proposed adder is used to design the modulo multiplier for less area and higher speed.