(Invited) Heterogeneous Integration As Enabler for Future Applications and Products

Future electronic systems like autonomous systems using high performance computing (HPC) and edge computing systems, sensor integrated systems and bio-integrated devices will required more and more functions which cannot be managed by a single chip, even if advanced SoC (System on Chip) concepts are used. Heterogeneous integration will be the next step and will pass beyond current SiP (System in Package) approaches. This concept of true heterogeneous integration is highly important for next-gen devices based on future CMOS-nodes, SiGe, SiC, III/Vs like GaAs or GaN and all different kinds of MEMS. Besides die and package stacking, embedding dies is a key technology for heterogeneous system integration. There are two main approaches for embedded die technologies: Fan-out Wafer and Panel Level integration, where dies are embedded into polymer encapsulants and Chip in Polymer, where dies are embedded into the substrate. Besides multiple die packaging also the integration of passive components as capacitors or resistors as well as the integration of shielding layers, antennas and e.g. resonators in and on package is a key for future applications. Co-design of chip and package for miniaturized heterogeneous packages will also give benefits especially for high frequency applications as 5G and beyond. The extension of advanced process design kits (PDK) towards packaging technologies including larger process tolerances and a much larger number of materials and processes would also support the approach of chip and package co-design. Another trend is moving from planar embedding technology to 3D shaped integration. Conformal electronics offer a functional shape adapted system with embedded electronics for e.g. sensors with aligned sensing direction, 3D shaped high frequency antennas or geometrically adapted electronics to the environment.