A Large-Swing High-Linearity Fully-Dynamic Amplifier With Automatic Calibration

In high-speed pipelined successive-approximation-register (SAR) analog-to-digital converters (ADCs), the residue amplifiers dominate the overall ADC speed, power, and accuracy. To improve the ADC performance, this brief proposes a large-swing high-linearity fully-dynamic open-loop amplifier. By setting the cascode input transistors in linear region, both the input/output swing and the linearity are improved significantly. By clamping the drain voltages of input transistors, the amplifier gain is PVT insensitive. These drain voltages of input transistors are clamped through a dynamic comparator with small size, which helps save energy. The comparator offset is automatically canceled out through a novel thermal-noise-based technique. Designed in a 40nm CMOS process, the proposed amplifier achieves an output swing of 400mVpp, a settling accuracy of 8-bit ENOB, and a voltage gain of 16X, under a 100MHz clock frequency. It is fully-dynamic and only consumes 1.15mW of power under a 1.1V supply. Compared to the state-of-the-art dynamic amplifiers, the output swing is increased by 4 times; the settling accuracy is improved by 2 bits; the voltage gain is increased by 4 times; the PVT sensitivity of voltage gain is reduced by 4.7 times; and the power consumption is decreased by 45% with fully-dynamic operation.