A Measurement-Based Method for Characterizing Parasitic Inductances in Power Electronic Circuits

This paper presents a new method of measuring parasitic inductances in various elements of power electronic circuits. The proposed solution features a low-cost design while providing accurate measurement results in a predefined range of stray inductances. The solution utilizes a unique parallel resonance circuit for extracting stray inductances in various circuits. Structural challenges as well as the analysis for the choice of circuit parameters are addressed in this study. Both simulation and experimental results are presented to exhibit the efficacy of the solution. Moreover, important design constraints that can affect the end results are explained and considered in the proposed experimental setup.