A 5.91-8.94GHz phase-locked loop in 65 nm CMOS for 5G applications

A low-noise fully-integrated charge-pump phase-locked loop (CPPLL) for 5G applications is presented in this letter. The PLL architecture includes a phase and frequency detector (PFD), a charge pump (CP), a low-pass filter (LPF), a voltage-controlled oscillator (VCO), and a programmable divider. To achieve low phase noise, class-C VCO, TSPC logic, and other methods are employed in the PLL circuit design. Fabricated in 65 nm technology, the PLL measures a tuning range of 5.91-8.94 GHz. The minimum and maximum measured phase noise are -125 dBc/Hz and -116.6 dBc/Hz @1 MHz. The size of CPPLL core area is 0.8 mm by 0.95 mm without the pads while having a 50-mW power consumption.