TSCL: A time–space crossing location for side-channel leakage detection

Cryptographic algorithms on devices are vulnerable to the so-called side-channel attacks(SCAs). The security evaluation of the cryptographic circuits is necessary to provide earlier leakage detection before manufacture. However, the complexity of locating leakage points is high because of the long execution time and the large scale of the circuit. To overcome this limitation, we propose an efficient leakage location method named time–space crossing location(TSCL) to locate the leakage in the hardware design, which combines the dynamic and static analysis. Unlike the traditional detection methods, we analyze the design features and power consumption characteristics of implementation to construct the candidate set on dynamic detection while further verifying candidate leakage points in the static detection stage. The t-test is known as a dynamic detection method to decrease the time of formal verification based on label propagation. The design features decrease the complexity of dynamic detection while the results of power consumption analysis promote static detection. We confirm the efficiency of the proposed method on unprotected and masking implementation of AES. Moreover, TSCL can be regarded as a third-party tool in the existing EDA tools of hardware design.