Transferable Graph Neural Network-Based Delay-Fault Localization for Monolithic 3-D ICs

2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)(2023)

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摘要
Monolithic 3-D (M3D) integration is a promising technology for achieving high performance and low-power consumption. However, the limitations of current M3D fabrication flows lead to performance degradation of devices in the top tier and unreliable interconnects between tiers. Fault localization at the tier level is therefore necessary to enhance yield learning, For example, tier-level localization can enable targeted diagnosis and process optimization efforts. In this article, we develop a graph neural network-based diagnosis framework to efficiently localize faults to a device tier. The proposed framework can be used to provide rapid feedback to the foundry and help enhance the quality of diagnosis reports generated by commercial tools. Results for four M3D benchmarks, with and without response compaction, show that the proposed solution achieves up to 32.86% improvement in diagnostic resolution with less than 1% loss of accuracy, compared to results from commercial tools. The proposed framework has also been demonstrated to be transferable to perform diagnosis on various design configurations without performance degradation.
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关键词
graph neural network-based delay-fault localization,Monolithic 3D integration,low power consumption,M3D fabrication,unreliable interconnects,tier-level localization,process optimization,graph neural network-based diagnosis framework,device tier,monolithic 3D ICs,M3D integration,commercial tools,response compaction,diagnostic resolution,yield learning enhancement,performance degradation
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