A 10-Gbps CTLE Design Using Split-Length Input Pair MOS Transistors
International Journal of Electronics Letters(2022)
摘要
The equaliser is an indispensable block inside the receiver in Serial Link systems. It is used to moderate the high-frequency loss of the signal in the channel. A new technique is described to improve the performance of the Continuous-Time Linear Equaliser (CTLE). This technique utilises split-length device (SLD) in order to boost the output impedance of the SLD. The proposed CTLE is designed and simulated in 65 nm CMOS technology. Post-layout simulation results demonstrate that the proposed technique has more peaking than conventional CTLE by an order of 1.5 dB at Nyquist frequency. The Proposed design has a vertical eye-opening of 220 mV and a horizontal eye-opening of 0.35 UI. It consumes 1.56 mW from a 1.2 V supply. A FoM of 13.1 fJ/bit/dB is achieved.
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关键词
split-length
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